Power conversion components, systems and methods

ABSTRACT

Components, systems and methods for generating variable frequency AC voltage from a DC power supply are described. The components include a full-bridge (FB) parallel load resonant (PLR) converter which operates in discontinuous conduction mode. The PLR converter includes MOSFETs in an H-bridge configuration and employs a topology which minimizes inductance. The PLR converter can be coupled to a single or poly-phase bridge for use as an inverter. The inverter can be used to produce an AC sinusoidal waveform from a low voltage, high current DC power supply. Systems and techniques for modulating the output from the PLR converter to produce an AC sinusoidal waveform having desired characteristics, including frequency and voltage, are also provided. The PLR converter can also be coupled to a rectifier for use as a DC-DC converter.

This application is a divisional application of U.S. patent application Ser. No. 11/132,205 which was filed on May 19, 2005 and has issued into U.S. Pat. No. 7,499,290. This application claims the benefit of Provisional U.S. Patent Application Ser. No. 60/572,234, filed May 19, 2004, the entirety of which is incorporated herein by reference.

This invention was made with United States Government support under Contract No. DASG60-00-C-0074, awarded by the United States Army Space and Missile Defense Command. The United States Government has certain rights in this invention.

BACKGROUND

1. Technical Field

The present application relates generally to power conversion and, in particular, to components, systems and methods for converting DC voltage and for generating variable frequency AC voltage from a DC voltage source.

2. Background of the Technology

According to one embodiment, a full-bridge (FB) parallel load resonant (PLR) converter is provided which operates in discontinuous conduction mode (DCM). References to parallel load resonant (PLR) converters can be found in the literature. The basic principle associated with the operation of PLR converter is to utilize the natural resonance of an L-C circuit for energy conversion. Current flowing through the device can be controlled using transistors arranged in various known topologies to regulate the cycles of a resonant waveform. The sinusoidal nature of a resonant waveform has the distinct advantage of allowing for zero current and/or zero voltage switching, which greatly reduces switching losses when compared to traditional pulse width modulation (PWM) techniques. Because “pulse width” is determined by the resonant frequency, voltage regulation is attained via frequency modulation.

Examples of PLR circuits are disclosed in U.S. Pat. Nos. 6,229,718 and 6,020,688, which patents are incorporated herein by reference. These circuits are used mostly in low power applications such as inverters for fluorescent lamp ballast. High efficiency, low voltage, wide load variation resonant converters have also been disclosed [1]. See also U.S. Pat. No. 6,483,731, which is incorporated herein by reference in its entirety. These resonant converters employ a multi-voltage resonant secondary to boost the output voltage.

According to further embodiments, also provided is a power inversion system and modulation techniques for use therewith wherein the system comprises a six-pulse inverter and a full-bridge (FB) parallel load resonant (PLR) converter operating in discontinuous conduction mode (DCM). DC-AC inverters are disclosed in U.S. Pat. Nos. 4,466,070; 4,862,342; 5,774,351; 5,889,668; and 6,519,168. AC-AC converters are disclosed in U.S. Pat. Nos. 4,942,511; 5,010,471; 5,270,914; and 6,839,249. In addition, switch-mode DC-AC inverters with a DC link are disclosed in references [2] and [3] and switch-mode DC-AC inverters with a high-frequency AC link and pulse width modulated (PWM) cycloconverters are disclosed in references [4-6] as well as in U.S. Pat. No. 6,700,803. Cycloconverters are systems that directly convert a higher frequency ac voltage to a lower frequency ac voltage. The inverters disclosed in these references generally involve square-wave bipolar or unipolar pulses with durations that are continuously variable. An objective of the methods disclosed in these references “ . . . [to] produce exactly the same waveforms as conventional PWM, while supporting HF links” [5]. Also, switch-mode DC-AC inverters with a high-frequency AC link and pulse width modulated (PWM) cycloconverters are disclosed in references [7-9]. The inverters described in these references invariably involve the rectification and impulse excitation of a low-pass filter with integral half-cycle sinusoidal, or quasi sinusoidal, voltages originating from a source of high-frequency AC voltage (meaning a waveform with zero average value which is transformable by a high-frequency transformer).

There still exists a need for improved power converters, particularly for conversion of low voltage DC power sources.

SUMMARY

According to a first embodiment, a circuit is provided which comprises:

a primary section adapted to receive a DC input;

a secondary section comprising a parallel capacitance resonance section and a rectifying section; and

a transformer coupling the primary and secondary sections;

wherein the primary section comprises a plurality of MOSFETs in an H-bridge configuration comprising a first group of MOSFETs on a first side of the bridge and a second group of MOSFETs on a second side of the bridge opposite the first side of the bridge;

wherein the input voltage is applied to the drain terminals of the first group of MOSFETs;

wherein the source terminals of the first group of MOSFETs, the drain terminals of the second group of MOSFETs and the primary side of the transformer are connected;

wherein the source terminals of the second group of MOSFETs are connected to form a return path for the current; and

wherein a parallel capacitance section is connected across the input.

According to a second embodiment, a converter is provided which comprises:

a circuit as set forth above further comprising a rectifying section connected to the transformer secondary, wherein the rectifying section comprises bidirectional switches in a single-phase or poly-phase bridge; and

a central controller which is adapted to control the bi-directional switches in the rectifying section.

According to a third embodiment, a power conversion method is provided which comprises:

generating a stream of alternating polarity pulses with a parallel-loaded resonant (PLR) inverter operating in discontinuous conduction mode;

rectifying the pulses using a single-phase or a poly-phase inverter bridge;

filtering the rectified pulses with a single phase or a poly phase low pass filter; and

generating a single-phase or poly-phase alternating current (AC) having a sinusoidal waveform;

wherein the alternating current having a sinusoidal waveform has a lower-frequency than the stream of alternating polarity pulses.

According to a fourth embodiment, a DC-AC converter is provided which comprises

a parallel-loaded resonant (PLR) inverter;

gate drivers associated with the PLR inverter;

a three-phase six-pulse bridge with bidirectional switches comprising power MOSFETs or power IGBTs;

gate drivers associated with the inverter bridge; and

a central controller comprising an FPGA, electronic memory, and associated analog and digital sensors and controls.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a primary layout for a full-bridge PLR converter.

FIG. 2 illustrates a simplified full bridge schematic.

FIG. 3 is a schematic of a system comprising a core PLR converter according to a further embodiment wherein a six-pulse bridge is used instead of output rectifiers to provide the inverter function and wherein a three-phase load is connected to terminals a-b-c.

FIG. 4 shows waveform definitions for the idealized resonant capacitor voltage, V_(r)(t), and the resonant capacitor current, I_(r)(t), for the core PLR converter of FIG. 3 operating in the discontinuous conduction mode.

FIG. 5 shows a conventional sinusoidal wave carrier modulation (SCWM) applied to a bipolar PWM in a DC link inverter.

FIGS. 6A and 6B illustrate a digitized SCWM applied to an inverter supplied by a PLR converter operating in discontinuous conduction mode showing in (a), V_(refA) intersecting the triangle wave in the second interval: i=2 and showing in (b), at some later time, V_(refA) intersecting the triangle in the fourth interval: i=3.

FIGS. 7A and 7B show the calculated normalized magnitude spectrum of the impulse time series resulting from the discrete SWCM algorithm for n=4, k=18, f_(l)=400 Hz, f_(r)=400 kHz, m_(a)=0.95 wherein a plot of the first 60 harmonics of f_(l) is shown in (a) and wherein a detail of the first 10 harmonics of f_(l) is shown in (b) and wherein ◯=line-to-neutral voltage and x=line-to-line voltage.

FIGS. 8A-8F show the results of simulated filtering by a second and fourth order Butterworth filter at each of three different line frequencies wherein, for each case, a phase voltage (V_(an)) and a line voltage (V_(ab)) is illustrated and wherein, in all cases, f_(c)=2 kHz and m_(a)=0.85 and wherein for each line frequency, n and k are the optimal selections listed in Table I.

FIG. 9 is a schematic layout of a DC-AC converter according to one embodiment showing gate drivers and a digital controller.

FIG. 10A shows actual PLR converter voltage waveforms.

FIG. 10B illustrates a sine function model of resonant capacitor voltage.

FIG. 10C illustrates an impulse function model of resonant capacitor voltage.

FIG. 11 is a control schematic showing the signal at various stages of the control process and also showing various algorithm options for the controller.

FIGS. 12A-12C illustrates the implementation of the SWCM algorithm wherein FIG. 12A shows the state vectors which describe all possible unit cells, FIG. 12B shows intersection of the carrier and reference in the fourth interval and FIG. 12C shows intersection of the carrier and reference in the second interval.

FIG. 13 illustrates the implementation of a digital controller employing a DSWCM algorithm.

FIGS. 14A-14C show the calculated line-line and line-neutral output voltage waveforms for a Butterworth 4^(th) order low pass filter with a 2 kHz cutoff frequency at 50 Hz (FIG. 14A), 60 Hz (FIG. 14B), and 400 Hz (FIG. 14C).

FIG. 15 is a schematic layout of a bridge converter with an AC link according to Reference [8].

DETAILED DESCRIPTION

According to one embodiment, the technology disclosed in this application relates to electrical energy conversion techniques for direct current (DC) voltage transformation where input power is low voltage and high current and wherein the output is high voltage. According to a further embodiment, the technology is related to high frequency (HF) alternating current (AC) signal generation. This technology has applicability for kilowatt class, high power density DC boost converters and as a high frequency AC source for HF link inverters. In particular, this technology has applicability for voltage conversion in vehicles where electrical power is generated by a low voltage alternator (typically 12 V or 28 V) as well as in the emerging 42 V technologies. However, this technology can also be used in any other applications where energy conversion is required for a low voltage, high power source.

According to one embodiment, the technology described herein is based on the concept of a full-bridge (FB) parallel load resonant (PLR) converter operating in discontinuous conduction mode (DCM). The technology makes use of the natural resonance associated with transformer leakage inductance and a capacitance in parallel with the output on the secondary side of the transformer. Proper utilization of this resonance produces very efficient energy conversion by reducing stress on the switching components.

Some basic principles of load resonant converter design are discussed below. The maximum load that a PLR converter can drive is determined by the natural impedance of the resonant circuit. This is calculated as follows: Zo=√{square root over (L _(r) /C _(r))} where L_(r) is the resonant inductance and in this case transformer leakage inductance and C_(r) is the resonant capacitance. The lower the ratio between the inductance and the capacitance the higher power that can be delivered to the load by the PLR converter [10].

In order to achieve high power density, high resonant frequencies are desired to reduce the size of passive components. Resonant frequency is determined by the following equation [10]:

$\omega_{0} = {\frac{1}{\sqrt{L_{r}C_{r}}}.}$

Another distinct advantage inherent to the design of a full-bridge PLR converter is the ability to incorporate several of the circuits non-idealities into the basic components of the device, namely the leakage inductance and intrawinding capacitance of the transformer [11-15]. These two parasitic elements are easily incorporated into a PLR boost converters resonant inductance and capacitance respectively.

According to one embodiment, as an effort to attain a minimal value for L_(r), the leakage inductance comprises the total value of the resonant inductor. This has the added effect of reducing the number of components as well as simplifying the layout. This aspect of the design also maximizes Z_(o) and ω_(o).

It has long been known that a current carrying conductor produces a magnetic field. Inductance is the measure of energy stored in such a magnetic field. The energy stored in a magnetic field can be defined as: E=½LI ² It is also known that for current flowing in an enclosed path of two parallel plates separated by air

$L = \frac{\mu_{0}A}{d}$ where μ_(o) is the permeability of free space, d is the width of the plates, and A is the cross-sectional area enclosed by the current path. This is to say that inductance of current flowing between two plates is dependent on the area enclosed by the current loop. Because of inductance current flowing through a conductor cannot change instantaneously. For a given potential (V) and inductance, the rate of change of current is defined as: V=Ldi/dt.

Given the preceding expressions, in order to design a converter capable of transforming high power at high frequency, inductance must be kept as low as possible. Achieving minimal inductance is all the more important for low input voltage systems. There is some discussion of minimizing inductance for high frequency converters found in the available literature. See, for example, U.S. Pat. Nos. 6,563,377 and 6,307,757, each of which is incorporated herein by reference in its entirety.

According to one embodiment, the present invention is directed to a full-bridge parallel load resonant (PLR) converter operating in discontinuous conduction mode. One of the advantages of this design in this particular mode of operation is the linear relationship between the converter output and the switching frequency [16]. In short, the control of this type of resonant converter is load independent. A detailed analysis of a full-bridge PLR converter in DCM can be found in the available literature [17].

According to one embodiment, a low input voltage, high power, high power density DC-DC boost converter is provided in a full bridge PLR topology by means of a lower inductance layout than could be previously achieved. According to a further embodiment, a high frequency AC voltage source is also provided which can be used in HF link inverters wherein the same low inductance layout can be achieved.

The total loop parasitic inductance of the converter can be utilized by making it one of the resonant components of the PLR topology. Utilizing the parasitic inductance inherent to the selected topology allows the size of the device to be reduced and losses associated with these non-idealities are abated.

As mentioned previously, inductance is dependent on the cross sectional area of the current path in any closed circuit. The present inventors sought to maximize power density for this converter through high frequency resonant operation. It has already been stated that the resonant frequency is the inverse of the square root of the product of the resonant capacitance and inductance and the natural impedance of the PLR converter is equal to (L_(r)/C_(r))^(1/2). Therefore, high power and high frequency in this type of converter can be achieved by minimizing the parasitic inductance. This can be achieved by minimizing the cross-sectional area of the current path on the primary side of the converter.

As set forth above, the topology of the PLR converter is in the family of converters referred to as full-bridge or H-bridge. FIG. 2 is a simplified schematic of the H-bridge configuration used for this design.

The output of the HF transformer can be center tapped. The hot-legs of the transformer secondary can be connected to a full-bridge rectifier and the center tap can serve as a neutral providing symmetrical positive and negative voltage with respect to this reference. The output of the rectifier circuit can also be fed into a two pole L-C filter to provide a low ripple DC output.

The implementation of a parallel load resonant converter as the power conversion topology for this device also makes it a valuable candidate for use as a high frequency AC source for an AC link inverter.

Power Converter Comprising a High Frequency AC Link and Power

Modulation Techniques for Use Therewith

The systems and methods described herein rectify and impulse excites a low-pass filter with AC voltage pulses with a zero average value. As set forth above, DC-AC inverters with a high-frequency AC link and pulse width modulated (PWM) cycloconverters have been disclosed which rectify and impulse excite a low-pass filter with AC voltage pulses with a zero average value [7-9]. However, the method of forming the high-frequency AC voltages differs from that described in these references in several important respects. In addition, the method of selecting the correct sequence of rectified integral half-cycle voltage waveforms required to generate the correct low-frequency AC voltage output from the filter also differs from that described in the references. As a result, the methods described herein have important advantages.

Moreover, the DC-AC inverters described in references [7-9] typically have a source of AC voltage that is continuous in waveform. These inverters also typically employ a PLR inverter operating in continuous conduction mode. Further, these inverters employ pulse density modulation as the algorithm for both selecting the sequence of rectified pulses and as the means for providing closed-loop feedback control of the output waveforms. Pulse density modulation as described in these references requires real time calculations, either of an analog or digital nature. Excessively complicated or unobtainable high-bandwidth processors are therefore required to implement this modulation in real time. This tends to limit applications to relatively low frequency AC-link sources (e.g., 20 kHz) [9].

In contrast, power inverters as described herein can employ significantly higher frequency AC-link sources (e.g., 400 kHz). Also, the AC link invariably involves a capacitor and an inductor in parallel to form a resonant “tank” circuit to support the AC link voltage under reactive power conditions. To maintain link voltage regulation, as quoted in reference [9] “ . . . power balance between the load and source must be done actively.” This involves additional control hardware that increases the system complexity and cost. Also, the systems and methods described herein have a source of AC voltage that is discontinuous in waveform. According to one embodiment, the systems comprise a PLR inverter operating in discontinuous conduction mode. Further, discretized sinusoidal waveform modulation is used as the algorithm for selecting the sequence of rectified pulses. Feedback control of the low-frequency output voltage requires only a low-bandwidth sensor and processor, which simply selects a “solution” to the algorithm with the correct amplitude duty factor. The discretized sinusoidal carrier wave modulation taught here can be implemented with calculations done by a realtime processor. Alternatively, multiple pre-calculated solutions representing different amplitude duty factors and/or different values of the fundamental frequency (e.g., 50, 60, and 400 Hz) can be stored in electronic memory. The least expensive, fastest controllers (e.g., FPGA's) can be used with the pre-calculated approach. Therefore, there is no practical limit on the frequency of the AC source voltage imposed by modern controller technology. The AC link invariably involves only a resonant capacitor. The link voltage (i.e., the resonant capacitor voltage) is inherently (i.e., passively) stable without active control. When the embodiment includes a PLR inverter with reasonably low equivalent series resistance, the link voltage regulation is excellent under all real and reactive power conditions.

A quantitative investigation was conducted into the most appropriate modulation technique to employ in the design of the Power Converter (ADPC). This investigation resulted in a decision to utilize digitally encoded sinusoidal carrier-wave modulation. Calculations suggest that this approach can be practically implemented with acceptable total harmonic distortion in the line-to-line output voltage by hardware that satisfies the following technical objectives:

To deliver 208 VAC (line-to-line), 3-phase power at an electronically selectable 50, 60, or 400 Hz.

To draw power from a 400-A, 28-VDC HMMWV alternator.

To achieve high power density through high conversion frequency and low part count.

To utilize a full bridge parallel load resonant converter in discontinuous conduction mode as a source of high-voltage (˜600 V peak) high-frequency (˜400 kHz) pulses.

Three techniques were investigated. They were:

State variable feedback controlling bipolar impulses applied to a phase-to-neutral LC filter.

Space Vector Modulation (SVM) of bipolar impulses applied to a phase-to-neutral LC filter.

Sinusoidal Carrier-Wave Modulation (SCWM) of bipolar impulses applied to a phase-to-neutral LC filter.

The first technique was judged less practicable because it requires high-bandwidth feedback and was rejected in favor of one of the other two techniques. SVM and SCWM are in the class of “pre-programmed” techniques and thus do not require high-bandwidth feedback.

SVM was also determined unsuitable for an inverter application which must act as a high quality line-frequency AC voltage source. However, the SVM approach was found to have attractive properties as a variable-frequency, variable-voltage motor drive (also known as a “Volt-Hertz scalar drive”) commonly used to drive variable-speed induction motors.

The systems and methods described herein can be used in mobile power systems that are compatible with existing U.S. Army vehicles. In particular, as a technology demonstration objective, the inventors are currently developing technology for converting 28 V DC electrical power common to the U.S. Army High Mobility Multi Wheeled Vehicle (HMMWV) into a power source useful for mobile air defense systems. The HMMWV is capable of accepting a specialized high-amperage alternator that can supply up to approximately 10 kW of electrical power. A standard version, rated at 28 VDC and 400 A, is manufactured by Niehoff and is available from the U.S. Army supply system. A research version, rated at 28 VDC and 500 A, has been acquired for research purposes by Mississippi State University (MSU).

The HMMWV has been used to provide power to the Army Short Range Air Defense (SHORAD) system. In the field, a 10-kW diesel motor generator powers the radar. A HMMWV tows the trailer-borne radar, while the diesel generator is accommodated in the bed of the HMMWV. The RPT program has already demonstrated that the 400-A alternator installed in a HMMWV can provide the necessary electrical power to operate the Sentinel radar. Currently, a two-stage conversion process representing prior art is required to power the radar. First, a DC-DC converter steps up the 28 VDC available from the alternator to 400 VDC. Second, a separate DC-AC inverter converts the 400 VDC to the 208-VAC, 3-phase, 400-Hz alternating current required by the radar.

According to the systems and methods described herein, the second separate DC-AC inverter can be eliminated by incorporating this function into the ADPC itself. In this manner, the functionality can be maintained while achieving a significant reduction (e.g., approximately 50%) in the size and weight of the overall power conversion system.

The modulation strategy is the algorithm to be applied to the inverter switches to convert the characteristic waveform produced by the PLR converter into the three-phase line-frequency voltage waveform required by the radar. Following this selection, it is possible to formulate performance specifications and to create a point design that establishes a number of internal specifications and component requirements. The modulation algorithm is well known to place fundamental limits on the signal amplitude available from a given input voltage and to drive the design of the filters required to achieve acceptable limits to harmonic distortion. Secondary questions, such as the maximum switch stress, cannot be answered until a basic technical approach is selected and a point design analyzed. The point design will, in turn, allow for specification of subcomponent ratings, such as switching transistors, transformers, and filter components. However, improper selection of the modulation approach can result in “can't get there from here” performance in key figures of merit, such as total harmonic distortion of the line-frequency output voltage. This matter must be reviewed carefully and quantitatively from first principles. That has now been accomplished; and the objective of this report is to document that effort.

Sinusoidal Carrier-Wave Modulation (SCWM)

Sinusoidal Carrier Wave Modulation (SCWM) is described below. In this section, the basic inverter topology will be introduced and critical waveforms defined. Mathematical treatment of the filter performance and spectral and temporal examples of the output voltage are also calculated.

SCWM is a well-known technique employed in both single phase and three phase pulse-width modulated inverters. A complete description of the basic operating principles can be found in [18]. In this application, it is assumed that a parallel loaded resonant (PLR) converter operating in the discontinuous conduction mode is supplying a continuous train of alternating polarity quasi-sinusoidal high-voltage pulses at a high repetition rate on the order of 400 kHz. A six-pulse inverter will deliver these pulses according to an appropriate modulation algorithm to three multi-pole passive filters connected to the three-phase load at the output. FIG. 3 illustrates the overall system concept. The result will be a low-THD line frequency sinusoidal voltage waveform that meets minimum specifications for a voltage source inverter. Adjusting the repetition rate of the high-frequency voltage pulses and/or other changes to the algorithm will allow the frequency of the three-phase sinusoidal output voltage to be electronically selectable.

Unlike the prior-art power converter described above, the high-frequency pulses will not be converted to a 400-V DC voltage first. Instead, the principle of the “high frequency AC link” will be employed [8]. However, there are significant differences between the approach analyzed here and that dominating the literature of high-frequency AC link converters, namely so-called pulse density modulation (PDM). PDM is different from SCWM, both in the method of SCWM described in the prior art and in the method proposed here. One liability of the AC link power converter is the requirement for bilateral switches in the six-pulse inverter. This arises because the link voltage can swing both positive and negative, so the switches must be capable of isolating either polarity from the output. Traditional semiconductor power switches suitable for the high frequency switching proposed here are capable of blocking only one polarity of applied voltage. However, several multiple-device combinations are possible which resolve this issue [7].

Waveform Definition

In the previous subsection, a specific system concept was revealed in FIG. 3 and general characteristics where assigned to the waveforms available to the inverter, but waveform specifics were omitted. This subsection provides that information.

The PLR converter delivers a quasi-sinusoidal (at no-load, perfectly sinusoidal) current pulse to the resonant capacitor which is shown in FIG. 3. FIG. 4 illustrates a typical, but idealized current pulse. The current pulse has a frequency of ω_(r), which is fixed by the magnitude of the resonant capacitance and by the equivalent series inductance of the PLR converter as seen by the capacitor reflected through a step-up transformer. A PLR converter produces a quasi-sinusoidal voltage across the resonant capacitor with a nominal frequency of ω_(r)/2. Each half sinusoid, or “haversine,” represents an impulse that can be applied through the half-bridge phase legs to impulse excite the output filters (and thus deliver or remove “volt-seconds” from the load). FIG. 4 illustrates the haversines and their relationship to the resonant current pulses. It should be noted that the resonant current pulses flow into the resonant capacitor only, but that the resulting voltage pulses can be switched to the load through the half-bridge phase legs. FIG. 4 also illustrates the switching period, which is defined by the period between resonant current pulses, which is also the time between haversines. The switching frequency ω_(s) is defined by this period as shown. The haversines alternate in polarity, but either polarity can be applied to the load with the same or opposite polarity (as required by the modulation algorithm) by appropriately selecting which switch in the half bridge is open or closed. The typical PLR resonant frequency is approximately 400 kHz. The peak resonant capacitor voltage V_(p) can be adjusted by changing the transformer turns ratio. A ratio of 21 produces a peak value just under 1200 V.

Modulation Algorithm

The specific SCWM algorithm is described below. This will be done in two parts. First, the classic method of prior art in which a sinusoidal control signal is sampled with a triangular “carrier wave” to form the PWM modulation envelope [18] is modified to produce an explicitly discrete second level of modulation compatible with the PLR converter pulse train. Second, a digital system for implementing the modulation algorithm is described which, among other methods, could be implemented with a programmable logic array (PLA) or its practical extension known as the field programmable gate array (FPGA).

Sinusoidal Carrier Wave Modulation (SCWM)

Conventional SCWM

The conventional SCWM technique is well known and is often applied to both single-phase and three-phase inverter applications [18]. It is an example of a “preprogrammed” modulation technique in that pulse width modulated output voltages coded with the SCWM technique are guaranteed to produce a waveform (following filtering), that is dominated by the fundamental (line-frequency) harmonic. Furthermore, in the analog version, undesirable harmonics in the unfiltered waveform begin near the sampling frequency provided that synchronous modulation is used. This can reduce the size of the output filter significantly when high sampling frequencies are used (which requires fast controllable switches in the six-pulse inverter bridge).

FIG. 5 defines the variables employed to code SCWM into a bipolar PWM voltage. If a DC link were used in FIG. 3 (instead of an AC link), the lower square-wave labeled “half-bridge output voltage” would be measured at any of the three half-bridge output nodes (nodes A, B, or C) measured with respect to the neutral node n. The upper two waveforms (reference signal and triangular carrier wave) exist in the PWM controller only. The two switches in each of the three half bridges are controlled by a comparator that monitors the value of the triangular carrier wave, V_(tri)(t), with respect to the sinusoidal reference signal, V_(ref)(t). The upper switch is closed and the lower switch is open when V_(tri)(t)<V_(ref)(t) such that V_(Xn)=+V_(dc)/2 (where X=A, B, or C). The switches are controlled into complementary states (upper switch open, lower switch closed) when V_(tri)(t)>V_(ref)(t) so that V_(Xn)=−V_(dc)/2. The result is the bipolar output pulse shown in FIG. 5, which is delivered to the output filter. The output filter, with a cutoff frequency above the fundamental harmonic, but below the higher-order switching harmonics, produces a reduced THD sinusoidal output voltage. Each half bridge is controlled by a different reference signal, with each reference signal delayed by a phase angle of 120° in order to produce conventional three-phase voltage waveforms.

Several important variables are defined in FIG. 5. The first is the conventional or analog sampling period T_(s), which is the period of the triangular carrier wave. From FIG. 5, we recognize that V_(tri)(t) intersects or “samples” V_(ref)(t) following the start of the triangular period. Assuming V_(tri)(t) and V_(ref)(t) are synchronized, then the two signals have a common delay given by an integer multiple of sampling periods, defined by the product of an integer j and T_(s). If the time reference frame is shifted to the beginning of each triangular wave such that t=τ−jT_(s), then:

$\begin{matrix} {{V_{tri} = \frac{t}{T_{s}/2}},} & (1) \end{matrix}$ for 0≦t≦T_(s)/2, and

$\begin{matrix} {{V_{ref} = \frac{{m_{a}{\sin\left\lbrack {\omega_{l}\left( {t + {j\; T_{s}}} \right)} \right\rbrack}} + 1}{2}},} & (2) \end{matrix}$ where m_(a) is the amplitude modulation factor and ω_(l) is the angular line frequency. Provided that m_(a) is in the linear range (0<m_(a)≦1), then V_(tri)(t) and V_(ref)(t) will intersect at one point each half period of V_(tri)(t). Equating (1) and (2)

$\begin{matrix} {\frac{t}{T_{s}/2} = \frac{{m_{a}{\sin\left\lbrack {\omega_{l}\left( {t + {j\; T_{s}}} \right)} \right\rbrack}} + 1}{2}} & (3) \end{matrix}$ permits the time at the point of intersection to be determined by solving the resulting Equation (3).

At this point we make an assumption, namely, that the sampling rate is relatively high, such that the change in the magnitude of Equation (2) over the short half period of the triangular wave is negligible (the conditions under which this is true will be derived next). If so, we can truncate the Taylor series expansion of the right hand side of (3) about jT_(s) to the second (linear) term:

$\begin{matrix} {\frac{t}{T_{s}/2} = {\frac{{m_{a}\left\lbrack {{\sin\left( {j\;\omega_{l}T_{s}} \right)} + {{\cos\left( {j\;\omega_{l}T_{s}} \right)}\omega_{l}t}} \right\rbrack} + 1}{2}.}} & (4) \end{matrix}$

It is customary for the sampling frequency to be a multiple of three with respect to the fundamental frequency of the reference signal. This ensures that the bipolar PWM signal will have odd symmetry. Selecting 12n samples during each period of the reference signal, where n is a non-zero integer, satisfies the triplet requirement and also allows the reference signal period to be divisible by two and four. Then

$\begin{matrix} {{{12\;{nT}_{s}} = \frac{2\;\pi}{\omega_{l}}},} & (5) \end{matrix}$ where 2π/ω_(l) is the period of the reference signal. Substituting (5) into (4) and solving for t yields:

$\begin{matrix} {{t = \frac{{m_{a}{\sin\left( {j\;\omega_{l}T_{s}} \right)}} + 1}{\omega_{l}\left\lbrack {\frac{24n}{\pi} - {m_{a}{\cos\left( {j\;\omega_{l}T_{s}} \right)}}} \right\rbrack}}{or}} & (6) \\ {t = {\frac{{m_{a}{\sin\left( {2\;\pi\frac{j}{12\; n}} \right)}} + 1}{\omega_{l}\left\lbrack {\frac{24\; n}{\pi} - {m_{a}{\cos\left( {2\;\pi\frac{j}{12\; n}} \right)}}} \right\rbrack}.}} & (7) \end{matrix}$

Equation (7) illustrates that there are only 3n discrete solutions for t, which proves that SCWM is a digitizing function. The condition that satisfies the approximation employed in (4) is that n>3.

In Equation (7), m_(a) is a continuous variable. While in the linear range (0<m_(a)≦1) the amplitude of the fundamental harmonic of the output voltage is directly proportional to m_(a), which can be written as [18] ({circumflex over (V)} _(xn))₁ =m _(a) V _(dc)/2,  (8) where ({circumflex over (V)}_(xn))₁ is the peak amplitude of the fundamental harmonic of the phase voltage V_(xn)(t) (where x=a, b, or c). The derivation of Equation (7) applies to an ideal analog modulator controlling an inverter with a constant dc input voltage. However, the device shown in FIG. 3 has a high frequency AC link, in which the voltage pulsates according to the illustrations in FIG. 4; therefore, in this case the additional analysis in the next section is required to understand how to apply SCWM. Discrete SCWM

The fundamental issue with synthesizing a low THD line-frequency sinusoidal voltage using the output of a PLR converter operating in the discontinuous conduction mode is that the output comes in discrete voltage pulses with fixed temporal shape (determined by ω_(r)) but adjustable pulse repetition frequency (determined by ω_(s)). Therefore, there is no need for the switches in the half bridge phase legs to modulate voltage, as was the case for the conventional dc link inverter of prior art. Instead, the half-bridge switches merely rectify, i.e., change the sign of, the voltage pulses. The advantage is that zero voltage switching is possible, which allows efficient, high conversion-frequency operation. In either case a filter is needed to isolate the inverter output (which should be sinusoidal) from the pulsating voltage supplied by the half bridge. To apply the fundamental SCWM technique, the AC link inverter supplies equivalent volt-seconds to the filter, and the PLR pulses are integrated whole (i.e., half-bridge switches cannot change state while the resonant capacitor voltage is non-zero).

The problem then boils down to integrating an integral number of PLR pulses in the output filter. The rules do impose some constraints. The PLR converter cannot dynamically change the resonant frequency or the amplitude of the resonant capacitor voltage. To maintain frequency stability at the output of the inverter, the switching frequency of the PLR converter is synchronized to the frequency of the reference signal.

Thus the SCWM controller is constrained to integrating a stream of pulses each delivering a fixed quantum of volt-seconds (area) at a fixed pulse repetition frequency (PRF). The only available degree of freedom is the polarity of each pulse, which can be changed on a pulse-by-pulse basis. This problem is similar to digitized SCWM, which has become popular in motor drives. In this case, the PRF of the PLR converter (ω_(s)) is equivalent to the sampling rate of the digital modulator, which is a different, higher sampling rate than that of the analog SCWM modulator (1/T_(s)). Prior to each PLR voltage pulse the digital SCWM controller must choose which polarity to switch to each of the three filters. The states of the half-bridge switches are set according to the polarities required by the algorithm and the polarity of the next voltage pulse, which alternates.

As shown in FIG. 6A, the decision is determined by the PWM envelope of the equivalent dc link inverter, which is in turn based on the usual intersection of the reference signal and the triangular carrier wave. However, because the switches cannot change state during a PLR voltage pulse, then the triangular wave must be partitioned or “digitized” into intervals, thus quantizing the effective pulse width of the envelope to accommodate integral numbers of pulses. In FIG. 6 we hypothesize that the PLR switching frequency is fixed such that a predetermined number of PLR pulses will be generated during each SCWM sampling period T_(s). Suppose the number of pulses is given by an integer k. For example, in FIG. 13, k=4. Also in FIG. 6, four (i.e., k) equal time intervals Δt between t=0 and t=T_(s)/2 are defined. The comparator problem is now simplified to determining in which time interval the reference signal intersects the triangle wave. The time interval Δt is defined as

$\begin{matrix} {{\Delta\; t} = {\frac{T_{s}/2}{k}.}} & (9) \end{matrix}$ Substituting (5) into (9) yields

$\begin{matrix} {{\Delta\; t} = {\frac{\pi}{12\;{nk}\;\omega_{l}}.}} & (10) \end{matrix}$ Equation (7) is normalized by dividing both sides by the Δt in (10):

$\begin{matrix} {\frac{t}{\Delta\; t} = {\frac{12\;{nk}}{\pi}{\frac{{m_{a}{\sin\left( {2\;\pi\frac{j}{12\; n}} \right)}} + 1}{\left\lbrack {\frac{24\; n}{\pi} - {m_{a}{\cos\left( {2\;\pi\frac{j}{12\; n}} \right)}}} \right\rbrack}.}}} & (11) \end{matrix}$ The interval on the triangle intersected by the reference signal is given by the value of t/Δt calculated from Equation (11) rounded off to the next higher integer.

The number of positive pulses switched to the filter during each SCWM sampling interval defines the state vector i. The number of negative pulses is simply k−i. The state vector is selected for each sampling interval by examination of Equation (11). To eliminate the possibility of a DC voltage at the output of the inverter, the impulse train, when averaged over one period of the fundamental, must have zero average value. This requires symmetry, which is ensured by selecting an even integer for k. In that case, i=k/2 is the state vector that delivers zero average volt-seconds to the filter. The algorithm for selecting the next state vector i is as follows. If t/Δt>k/2, then i equals the integer calculated by rounding t/Δt down to the next lower integer. If t/Δt<k/2, then i equals the integer calculated by rounding t/Δt up to the next higher integer. This algorithm automatically accommodates overmodulation (m_(a)>1), with the limiting result being square-wave operation as expected.

FIG. 6A illustrates for the k=4 example the pulse train switched to node A by the controller when i=2. FIG. 6B illustrates the pulse train switched to node A by the same controller when i=3. In this example, when an odd number of positive pulses are required, i/2+1 positive pulses are delivered first, followed by the k—i negative pulses, and finishing with the remaining i/2−1 pulses. This approach approximates the symmetry of analog SCWM.

Selecting n and k

An integral number of PLR converter pulses must fit within one period of the reference signal, indeed, the total duration of the pulse train over the longest non-repeating interval defines the frequency of the fundamental, which for the inverter can be exactly equal to either 50 Hz, 60 Hz, or 400 Hz. This is achieved by selecting n and k and the switching frequency ω_(s) to fix the longest non-repeating interval exactly equal to the period of the line-frequency reference signal T₁=2π/ω_(l). The proper relationship is determined by substituting Δt=π/ω_(s) into Equation (10), resulting in:

$\begin{matrix} {{12\;{nk}\frac{\pi}{\omega_{s}}} = {\frac{\pi}{\omega_{l}}.}} & (12) \end{matrix}$ Which becomes:

$\begin{matrix} {{{12\;{nk}} = {\frac{\omega_{s}}{\omega_{l}} = {\frac{\omega_{s}}{\omega_{r}}\frac{\omega_{r}}{\omega_{l}}}}},} & (13) \end{matrix}$ where ω_(r) is the resonant frequency of the PLR converter. Since ω_(r) is fixed, the ratio ω_(r)/ω_(l) will take on one of three values corresponding to the three line frequencies. For discontinuous operation of the PLR converter ω_(s)/ω_(r)<1, so ω_(r)/ω_(l) represents the largest possible number of PLR impulses per line-frequency period. To satisfy (13) the switching frequency must be selected to ensure that ω_(s)/ω_(l) is an integer. Therefore, unlike the control of a DC-DC PLR converter of prior art in which the regulation of the output voltage is maintained by adjusting ω_(s)/ω_(r), in the invention taught here this ratio is fixed at any value of line frequency by the product of n and k.

Digitizing the amplitude of the reference signal introduces a new source of distortion in the filtered output signal that does not exist with conventional analog SCWM. The problem is similar to that of digitally recording an audio signal. The effective sampling frequency, specified by the integer 12n, must exceed the bandwidth of the “baseband” (reference) signal. For low THD digital recording the number of bits of resolution of the analog-to-digital converter must be large to accurately resolve the amplitude of the signal at each sampling instant. Similarly, the integer k represents the amplitude resolution of the discrete SCWM algorithm. Ideally both 12n and k should be large, but their product is limited by Equation (13). The selection of a particular set of individual values for n and k should minimize the total harmonic distortion of the filtered output voltage.

A MATLAB program has been written that models a high-frequency link inverter fed with voltage impulses from a PLR converter operating at constant switching frequency. The program calculates the Fourier Transform of a series of delta functions (i.e., unit impulse functions) delivered to the input of the filter at equally spaced time intervals. Each impulse has the same volt-second product, but either a positive or negative sign as dictated by the discrete SCWM algorithm. The Fourier Transform of a time series of impulses delivered to node A, to node B, and the difference between node A and B is computed, so that the harmonic content of the line-to-neutral (“phase”) voltage and the line-to-line (“line”) voltage can be estimated. An example of the harmonic spectrum of the time series of impulses generated by the discrete SWCM algorithm for a particular point design in which f₁=ω_(l)/2π=400 Hz, ω_(r)/ω_(l)=1000 (i.e., f_(r)=ω_(r)/2π=400 kHz), n=4, and k=18 is shown in FIG. 7. The harmonics for both the phase voltage and the line voltage are shown. The line-to-line voltage contains no third order harmonics, as would be expected for a three-phase line-to-line voltage. There are two sources of distortion in the output waveform. First, there are the significant harmonics created by the sampling process, which are centered at or near the sampling frequency harmonic 2π/ω_(l)T_(s)=12n=48, and which are clearly observed in FIG. 7A. These are expected, as they are also present in conventional analog SCWM [18]. A second source of unwanted harmonics is the digitization of the triangle carrier wave, which, like square wave modulation, can produce significant low-order harmonics (i.e., 1<h<12n). Fortunately, the harmonics can be minimized by optimal selection of n and k, as for example illustrated in FIG. 7B; where the harmonics below 10 are very small as compared to square wave modulation. Nevertheless, the 7^(th) harmonic is not negligible. Depending on the output voltage THD specification, these low-order harmonics may require filtering along with the sampling frequency harmonics.

Optimizing the selection of n and k for minimum THD requires specifying the harmonics that remain in the pass band of the output filter. An ideal low-pass filter with a cutoff frequency ω_(c) is assumed. All harmonics h=ω/ω_(l) greater than ω_(c)/ω_(l) are eliminated by the ideal filter. The remaining harmonics below ω_(c)/ω_(l) are in the pass band and contribute to the total harmonic distortion of the waveform at the output node of the filter. The program calculates the THD of the phase voltage and the line voltage as a function of n and k. The combination that produces the lowest THD is a candidate for implementation in the inverter. The procedure has been applied to all three line frequencies. Because the line frequency is expected to be electronically selectable, but it is not practical for the power filters to be electronically adaptable, a single stationary filter cutoff frequency is assumed. This forces ω_(c) to fall within a limited range safely above the highest line frequency (400 Hz), but usefully below the lowest sampling frequency. The additional requirement to filter troublesome low order harmonics restricts the range of ω_(c) to that illustrated in FIG. 14( b). The THD's at the optimal selections for n and k for the three line frequencies are contained in Table I for two different filter cutoff frequencies (f_(c)=2π/ω_(c)=2 kHz and 4 kHz). Optimization was performed at the higher cutoff frequency and the largest integer value of 12nk consistent with satisfying the condition ω_(s)/ω_(r)≦0.9 to allow for blanking time while switching the PLR converter H-bridge.

TABLE I Results of Optimized Selection of n and k at Three Line Frequencies. THD_(a) Applies to the Phase Voltage, THD_(ab) Applies to the Line Voltage and for All Calculations m_(a) = 0.95 THD_(ab) f₁ [Hz] f_(c) [kHz] ω_(c)/ω₁ n k THD_(a) [%] [%] 50 2 40 8 74 1.30 1.04 60 34 6 80 1.39 1.09 400 5 4 18 0.23 0.19 50 4 80 8 74 1.86 1.48 60 68 6 80 2.01 1.65 400 10 4 18 2.05 1.93 Amplitude Scaling

Two additional design variables are the PLR converter transformer turns ratio a=N_(p)/N_(s) and the amplitude duty factor m_(a). They should both be selected carefully since the inverter must synchronize ω_(s) to the line frequency reference signal to satisfy Equation (13). In theory the lost degree of freedom is made up with m_(a), which is continuously adjustable over a large linear range (0→1). But in practice disturbing m_(a) too much from the value at which n and k were optimized invites additional harmonic distortion. Obviously, the transformer turns ratio, once selected, is not adjustable. Fortunately, the output of most likely input voltage sources, such as an automobile alternator, is regulated and can be expected to stay within a few percent of nominal while the engine is running. Only if the engine or alternator fails is a larger deviation likely and then down to the nominal output voltage of the battery. The open-loop voltage regulation of the PLR converter itself is good (a characteristic of this type of converter). To calculate the turns ratio and, incidentally, to determine the minimum blocking voltage of the inverter transistors, a formula for amplitude scaling applicable to SCWM must first be derived.

A formula applicable to conventional analog SCWM is known that relates the RMS line voltage to the dc link voltage. The formula is given in [18, p. 228] as:

$\begin{matrix} {V_{LL} = {m_{a}\sqrt{\frac{3}{2}}{\frac{V_{dc}}{2}.}}} & (14) \end{matrix}$

To apply this formula, a second formula equating the average value of the high-frequency AC link voltage to V_(dc) is required. From FIG. 4 the resonant capacitor voltage is approximated as:

$\begin{matrix} {{V_{r}(t)} = {V_{p}{{\sin\left( {\frac{\omega_{r}}{2}t} \right)}\ .}}} & (15) \end{matrix}$ And the value averaged over one switching period 2π/ω_(s) is given by:

$\begin{matrix} {\left\langle {V_{r}(t)} \right\rangle = {\frac{\omega_{s}}{2\;\pi}{\int_{0}^{2\;{\pi/\omega_{r}}}{V_{p}{\sin\left( {\frac{\omega_{r}}{2}t} \right)}\ {{\mathbb{d}t}.}}}}} & (16) \end{matrix}$ Evaluating (16) leaves:

$\begin{matrix} {\left\langle {V_{r}(t)} \right\rangle = {{\frac{\omega_{s}}{2\;\pi}\frac{2}{\omega_{r}}{V_{p}\left\lbrack {- {\cos\left( {\frac{\omega_{r}}{2}t} \right)}}\  \right\rbrack}_{0}^{2\;{\pi/\omega_{r}}}} = {{\frac{\omega_{s}}{2\;\pi}\frac{4}{\omega_{r}}V_{p}} = {\frac{2}{\pi}\frac{\omega_{s}}{\omega_{r}}V_{p}}}}} & (17) \end{matrix}$

For large values of k both types of link converters (analog SCWM or digitized SCWM) deliver approximately the same volt-seconds over one sampling period (meaning only small differences result from the digitization of the triangular carrier wave); thus justifying equating the resonant capacitor voltage averaged over one switching period to the DC link voltage,

V _(r)(t)

=V _(dc).  (18)

Equation (14) can now be applied to the discrete SCWM algorithm. Equation (19) results:

$\begin{matrix} {V_{LL} = {m_{a}\sqrt{\frac{3}{2}}\frac{V_{p}}{\pi}{\frac{\omega_{s}}{\omega_{r}}.}}} & (19) \end{matrix}$

Equation (19) is useful because it relates an essential output specification, the line-to-line RMS voltage V_(LL), to the peak AC link voltage V_(p), which in turn allows the minimum peak blocking voltage of the inverter transistors to be specified and the transformer turns ratio to be calculated.

A point design is now offered that assumes the nominal DC input voltage is 28 V; the nominal AC line voltage is 208 V RMS; and a converter adjustability of +10% is adequate over the load range of the converter. Thus the amplitude duty factor range is 0.85<m_(a)<0.95. Table II provides the results of the solution of (19) for V_(p) and includes an estimate for the THD at each line frequency. The largest peak voltage in Table II should be used as a guide to selecting semiconductor devices for the inverter bridge and for selecting the transformer turns ratio. The point design assumes that voltage droop resulting from loading of the PLR converter is managed by increasing m_(a) to the limit of 0.95 at full load, thus ensuring that minimum THD is reached at full load. The turns ratio is selected based on low-load conditions (m_(a)=0.85) and the effective nominal input voltage. In an ideal PLR converter, the peak resonant capacitor voltage is double the dc input voltage; therefore, the effective nominal input voltage is 2×28 V=56 V.

$\begin{matrix} {\frac{N_{S}}{N_{P}} = {{\frac{1}{a} \geq \frac{726\mspace{14mu} V}{56\mspace{14mu} V}} = 13.}} & (20) \end{matrix}$

To derive a neutral, the actual turns ratio should be an even number to allow for a center tap. It should also be greater than the minimum to allow for a non-ideal resonant gain (i.e., less than 2). Candidate values for 1/a include 14, 16, and 18. Losing the alternator or the engine will produce a 16% reduction in input voltage (to approximately 24 V); but this will likely result in no more than a 10% reduction in RMS line voltage under typical load conditions, which is consistent with utility-grade electrical power.

TABLE II Amplitude Scaling the Inverter Point Design (m_(a) = 0.85 for All Calculations) THD_(a) THD_(ab)  f₁ [Hz] ω_(c)/ω₁ [%] [%] ω_(s)/ω_(r) V_(p) [V] 400 5 1.22 0.41 0.864 726 50 40 1.19 1.01 0.880 713 60 34 1.67 1.59 0.864 726 Filter Design

The filter assumed in the calculations contained in Tables I and II is ideal, and thus it is not realizable. A realizable filter that does not overly compromise the point design is desired. Given the relative close proximity of the cutoff frequency to the 400 Hz line frequency, a maximally flat filter profile is desirable; such a profile will prevent additional harmonic distortion caused by pass band ripple. In this case, a Butterworth filter is the choice, although other filter realizations are possible, and these teachings will prompt those schooled in the art to the many possibilities. Considering size and component count, the lowest order filter that satisfies the following requirements is desirable:

1. When f_(l)=400 Hz, minimal pass band attenuation because ω_(c)/ω_(l) is only 5.

2. When f_(l)=50 or 60 Hz, maximal attenuation at 2π/ω_(l)T_(s)=12k=96 or 72, respectively, because ω_(c)/ω_(l) is quite close at 40 and 34, respectively.

The first requirement is “common sense.” The second requirement is a consequence of the optimized selections for n and k, which cause the sampling frequency to be close to the filter cutoff frequency. The filter cutoff frequency cannot be decreased because of the first requirement. Together, both requirements are best satisfied by the highest filter order practicable. Given the requirements and the size constraints, only a second or fourth order filter is worth considering.

A MATLAB program has been written that implements both second and fourth order Butterworth filter polynomials to examine the time-domain output of such filters excited by a time series of impulse functions implementing the optimized discrete SCWM algorithm. FIGS. 8A-8F illustrate the results of six simulations that predict the waveforms produced at the output of the ADPC using both a second and fourth order filter, each with the same cutoff frequency f_(c)=2 kHz. At f₁=400 Hz, there is little difference between the two filters. However, at the two lower line frequencies, the influence of the proximity of the sampling frequency to the filter cut off frequency becomes apparent. Clearly, the second-order filter roll-off (−40 dB/dec.) is inadequate to filter the sampling frequency harmonics. In contrast, the fourth-order filter, at least subjectively, produces a waveform clear of significant ripple arising from the sampling frequency harmonics. From this analysis, a fourth-order Butterworth low-pass filter is recommended over a second-order filter.

FIG. 9 is a schematic layout of a prototype DC-AC converter according to one embodiment. The converter includes a PLR converter with an H-bridge configuration, a transformer, and three half-bridges connected to the transformer secondary. A digital controller and gate drivers are used to control the output.

FIG. 10A shows actual PLR converter voltage waveforms. FIG. 10B illustrates a sine function model of resonant capacitor voltage and FIG. 10C illustrates an impulse function model of resonant capacitor voltage.

FIG. 11 is a control schematic showing the signal at various stages of the control process. Also shown in FIG. 11 are various algorithm options for the controller. These options include feedback control and preprogrammed control. Modulation strategies for preprogrammed control include Space Vector Modulation (SVM) and Sine Carrier Wave Modulation (SCWM).

In conventional “analog” SCWM, a triangular carrier wave samples a sinusoidal reference at a frequency 1/T_(s), where T_(s) is the sampling interval. As shown in FIG. 3, the intersection of the carrier and reference voltages determines the resulting pulse width modulation. In discrete Sine Carrier Wave Modulation (DSCWM), the following process is employed:

Select an integer n to divide the line-frequency period by exactly 12 n sampling intervals: T_(s)=(2π/ωline)/(12 n). The effective sampling frequency=12nω_(line).

The PLR converter switching frequency ω_(s) is locked (this is easily accomplished in the digital controller) so that exactly k impulses occur during one sampling interval: k=T_(s)/(2π/ω_(s)).

k+1 unit cells are defined that allow the k impulses in each sampling interval to be organized into the k+1 combinations with a unique volt-second product.

The triangular carrier wave is divided into k intervals.

Based on the interval on the triangle intersected by the reference voltage, one of the k+1 unit cells is selected and switched by the half-bridge to the filter.

FIGS. 12A-12C illustrates the implementation of a DSWCM algorithm. In this algorithm, five three-bit words (W₀-W₄), called state vectors, describe all possible unit cells. The state vectors are shown in FIG. 12A. In FIG. 12B, V_(refA), the sinusoidal reference voltage for phase A, intersects the triangular carrier wave in the fourth interval. The state vector corresponding to i=3 is selected (rounding down while above the median at i=2). In FIG. 12B, V_(refA) intersects the second interval. The state vector corresponding to i=2 is selected (rounding up while below the median). State vectors W₀ and W₄ are reserved for overmodulation (m_(a)>1).

FIG. 13 illustrates the implementation of a digital controller. State vectors defining the sequence of unit cells to be switched to the filter for each phase (A, B and C) are precomputed and stored in memory for a range of amplitude duty factors at each line frequency. Decode logic provides digital signals setting the logic states of all switches in both the converter H-bridge and the inverter half bridges. A master clock provides line frequency time reference and system synchronization. “Divide by” counters down shift the clock frequency to lock the converter switching frequency and the inverter sampling frequency.

In designing the filter, various constraints are present. The constraints can be broadly classified as either physical constraints or spectral constraints. Physical Constraints are set forth below:

The filter order should be as low as possible to reduce the part count.

The filter cutoff frequency should be as large as possible to reduce the size of the parts.

Spectral Constraints are set forth below:

The cutoff frequency should be below the sampling frequency to eliminate switching harmonics.

The cutoff frequency should be above the largest line frequency.

The pass band should be reasonably flat to avoid amplifying low-order harmonics in the pass band.

Roll off should be monotonic so that there is adequate attenuation of switching harmonics in the stop band.

A filter design addressing these constraints has been implemented by:

Optimizing selection of n and k at each line frequency to minimize low-order harmonics.

Select the cutoff frequency=2 kHz to minimize Total Harmonic Distortion (THD) @ f_(line)=400 Hz due to 7th harmonic.

Selecting a 4th order Butterworth low-pass filter to adequately attenuate sampling frequency harmonics beginning at 4.8 kHz and 4.3 kHz for 50 and 60 Hz line frequencies, respectively, and to avoid pass- and stop-band ripple.

FIGS. 14A-14C show the calculated line-line and line-neutral output voltage waveforms for a Butterworth 4^(th) order low pass filter with a 2-kHz cutoff frequency. THD was calculated assuming optimal n and k at each line frequency and m_(a)=0.85.

Key factors influencing the specifications are:

Switching frequency to resonant frequency ratio, ω_(s)/ω_(r)<90% to provide blanking time for switching.

Amplitude duty factor at nominal (50%) load, (m_(a))_(nom)=0.85 to provide acceptable THD, and ±5% margin for losses between light load and rated load.

DC input voltage: (V_(in))_(nom)=28 V, (V_(in))_(min)=24 V to enable short-duration UPS function off of truck batteries.

Nominal line-line output voltage=208 Vrms ±10% which is equivalent to utility service.

Rated output power=5.6 kW, short duration overload=7 kW. Rated line current at 90% nominal output voltage=17 Arms.

Key specifications are:

Transformer turns ratio: 14 N_(s)/N_(p)≦18.

Half-bridge switch voltage, BV_(DS)≧800V.

Half-bridge switch current, ID_(SS)≧30 A.

FIG. 15 is a schematic layout of a bridge converter with an AC link according to Reference [8].

While the foregoing specification teaches the principles of the present invention, with examples provided for the purpose of illustration, it will be appreciated by one skilled in the art from reading this disclosure that various changes in form and detail can be made without departing from the true scope of the invention.

REFERENCES

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1. A power conversion method comprising: generating a stream of alternating polarity pulses with a parallel-loaded resonant (PLR) inverter operating in discontinuous conduction mode; inverting the pulses using a plurality of bi-directional switches and a single-phase or a poly-phase inverter bridge; filtering the inverted pulses with a single phase or a poly phase low pass filter; and generating a single-phase or poly-phase alternating current (AC) having a sinusoidal waveform; wherein the alternating current having a sinusoidal waveform has a lower frequency than the stream of alternating polarity pulses.
 2. The method of claim 1, wherein the pulses are inverted by a three-phase inverter bridge.
 3. The method of claim 1, further comprising controlling the positions of the switches during inverting to generate the AC sinusoidal waveform.
 4. The method of claim 3, wherein the positions of the switches are determined by a central controller.
 5. The method of claim 4, wherein the central controller uses a discretized carrier wave modulation algorithm to determine the positions of the switches.
 6. The method of claim 1, further comprising: determining or selecting a sequence of pulses which produces an AC sinusoidal waveform having a desired voltage; and varying the sequence of pulses generated by the PLR inverter to achieve the desired voltage.
 7. The method of claim 6, wherein the sequence of pulses is either determined in realtime using a modulation algorithm or is selected from a pre-calculated electronically stored look-up table.
 8. The method of claim 4, wherein the central controller is a field programmable gate array (FPGA) which uses a look-up table stored in electronic memory to implement the pre-calculated discretized carrier wave modulation algorithm.
 9. The method of claim 1, wherein the PLR inverter is bi-directional in power flow.
 10. The method of claim 1, wherein the PLR inverter comprises a high-frequency AC-link.
 11. The method of claim 1, wherein the PLR inverter comprises-a resonant capacitor having a voltage which is inherently stable under real and reactive power flow.
 12. The method of claim 1, wherein the PLR inverter comprises the circuit of claim
 1. 13. A DC-AC converter comprising: a PLR inverter configured to operate in a discontinuous conduction mode; gate drivers associated with the PLR inverter; a three-phase six-pulse bridge with bi-directional switches comprising power transistors associated with the PLR inverter; gate drivers associated with the pulse bridge; and a central controller comprising FPGA, an electronic memory, analog sensors and digital sensors, the controller being configured to control the DC-AC converter.
 14. The DC-AC converter of claim 13, further comprising a low pass filter.
 15. The DC-AC converter of claim 13, wherein the converter produces a 208 V AC, three-phase voltage waveform and supplies up to 10 kVA of apparent power comprising any self-consistent combinations of real and reactive components at 50-Hz, 60-Hz, or 400-Hz.
 16. The DC-AC converter of claim 13, wherein the power transistors are power MOSFETs.
 17. The DC-AC converter of claim 13, wherein the power transistors are power IGBTs. 